PA communication chip board

Features

FBC0409 is designed for fieldbus physical and part data link communication functions, details list below:

Supports line data rate 31.25K Bit/S

Build-in Manchester Encoder/Decoder

Transmitter Jibber inhibit, receiver super long frame inhibit

Automatic parity recognize and correct

Message type and destination address detection automatically

Automatic transmitter and receiver frame check

Build-in three channels DMA controller，used to control data transmitting, receiving and address recognization looking up table memory management

4k bytes asynchronous SRAM internal as communication buffer for transmitting, receiving and address lookup table memory

Length of Preamble, Start and Stop delimiter under software controlled

Build-in bus arbiter, CPU accessing internal SRAM correctly

Data link layer timer ( 1ms、1/32 ms、octet time timer )

Designed lots of useful interrupt and status Registers

Compatibility with INTEL、ARM serials CPU

Internal loop back for test

STANDBY feature

Power supply: 2.7～5.5V

Power consumption: <600uA </span>

Operating temperature range: -40℃～85℃

Available in 44-pins TQFP package

Designed to comply with IEC 61158-2

Supports line data rate 31.2Skbit/s

Good at integration, simple external circuit, small size

Available in 44-pin TQFP package

Low power consumption design : <600µA</span>

Performance Characteristic

Supports line data rate 31.25K BIT/S

Build-in Manchester Encoder/Decoder

Transmitter Jibber inhibit, receiver super long frame inhibit

Automatic parity recognition and correction

Build-in two channels DMA controller，used to control data transmitting, receiving and address recognition

Build-in bus arbiter, CPU accessing internal SRAM correctly

Internal loop back for test

Operating temperature：-40℃～85℃

Typical Application

Chip FBC0409 was designed as fieldbus communication controller, following is its typical application.